`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:01:09 09/27/2012 
// Design Name: 
// Module Name:    binarybcd 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module binarybcd(num_i,num_o,clk_i
    );

	input clk_i;
	input [3:0] num_i;
	output [4:0] num_o;
	reg [4:0] num_o;
	
	always@ (posedge clk_i)
		case (num_i)
            4'b0000   : num_o <= 5'b10000;
            4'b0001   : num_o <= 5'b10001;
            4'b0010   : num_o <= 5'b10010;
            4'b0011   : num_o <= 5'b10011;
            4'b0100   : num_o <= 5'b10100;
            4'b0101   : num_o <= 5'b10101;
            4'b0110   : num_o <= 5'b10110;
            4'b0111   : num_o <= 5'b10111;
				4'b1000   : num_o <= 5'b11000;
            4'b1001   : num_o <= 5'b11001;
            4'b1010   : num_o <= 5'b00000;
            4'b1011   : num_o <= 5'b00001;
				4'b1100   : num_o <= 5'b00010;
            4'b1101   : num_o <= 5'b00011;
            4'b1110   : num_o <= 5'b00100;
            4'b1111   : num_o <= 5'b00101;
				default : num_o <= 5'b10000;
         endcase	

endmodule
